Jinseong Heo

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Despite several years of research into graphene electronics, sufficient on/off current ratio I(on)/I(off) in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and(More)
Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer(More)
The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods(More)
All Rights Reserved iii To my mother and my late father iv Acknowledgements It is hard to compress six years of a journey into a couple of pages, but let me give it a shot anyway. I should begin by thanking the person who influenced this thesis the most, my advisor Prof. Marc Bockrath—for taking me on as a curious-but-mostly-clueless engineer, showing faith(More)
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