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—Clock tree synthesis plays an important role on the total performance of chip. Gated clock tree is an effective approach to reduce the dynamic power usage. In this paper, two novel gated clock tree synthesizers, power-aware clock tree synthesizer (PACTS) and power-and slew-aware clock tree synthesizer (PSACTS), are proposed with zero skew achieved based on(More)
In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Voltage and Temperature) variations contribute a lot to its behavior. Previous works mainly focused on skew and wirelength minimization. It may lead to negative influence towards these process(More)
Routability optimization has become a major concern in physical design of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominant factor of the overall performance of a circuit. In order to optimize interconnect cost, we need a good congestion estimation method to predict routability in the early designing stages.(More)
—Global routing remains a fundamental physical design problem. We observe that large circuits cause high memory cost 1 , and modern routers could not optimize the routing path of each two-pin subnet. In this paper, (1) we develop a dynamic topology update technique to improve routing quality (2) we improve the memory efficiency with negligible performance(More)
ePlace is a generalized analytic algorithm to handle large-scale standard-cell and mixed-size placement. We use a novel density function based on electrostatics to remove overlap and Nesterov's method to minimize the nonlinear cost. Steplength is estimated as the inverse of Lipschitz constant, which is determined by our dynamic prediction and backtracking(More)
—Recent advances in three-dimensional integrated circuits (3D-ICs) offer a new dimension of design exploration at traditional physical architecture of datapath components. The emerging monolithic inter-tier vias (MIVs) provides more advantages over through-silicon vias (TSVs) in terms of higher integration density and lower design overhead. In this work, we(More)
Internet of Things (IoT) is playing a more and more important role after its showing up, it covers from traditional equipment to general household objects such as WSNs and RFID. With the great potential of IoT, there come all kinds of challenges. This paper focuses on the security problems among all other challenges. As IoT is built on the basis of the(More)
— We propose a flat nonlinear placement algorithm FFTPL using fast Fourier transform for density equalization. The placement instance is modeled as an electrostatic system with the analogy of density cost to the potential energy. A well-defined Poisson's equation is proposed for gradient and cost computation. Our placer outperforms state-of-the-art placers(More)
We develop a flat, analytic, and nonlinear placement algorithm, <i>ePlace</i>, which is more effective, generalized, simpler, and faster than previous works. Based on the analogy between placement instance and electrostatic system, we develop a novel placement density function <i>eDensity</i>, which models every object as positive charge and the density(More)
As the complexity of physical implementation continues to grow with technology scaling, routability has emerged as a major concern and implementation flow bottleneck. Infeasibility of routing forces a loop back to placement, netlist optimization, or even RTL design and floorplanning. Thus, to maintain convergence and a manageable number of iterations in the(More)