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Energy-aware mapping for tile-based NoC architectures under performance constraints
TLDR
In this paper, we present an algorithm which automatically maps the IPs/cores onto a generic regular Network on Chip (NoC) architecture such that the total communication energy is minimized. Expand
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Energy- and performance-aware mapping for regular NoC architectures
TLDR
In this paper, we present an algorithm which automatically maps a given set of intellectual property onto a generic regular network-on-chip (NoC) architecture and constructs a deadlock-free deterministic routing function such that the total communication energy is minimized. Expand
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DyAD - smart routing for networks-on-chip
TLDR
We present and evaluate a novel routing scheme called DyAD which combines the advantages of both deterministic and adaptive routing schemes. Expand
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Key research problems in NoC design: a holistic perspective
TLDR
We provide a general description for NoC architectures and applications and then enumerate several outstanding research problems (denoted by P1-P8) organized under three topics: communication infrastructure synthesis, communication paradigm selection, and application mapping optimization. Expand
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System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
TLDR
In this paper, a novel system-level buffer planning algorithm that can be used to customize the router design in networks-on-chip (NoCs) is presented. Expand
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Architecting voltage islands in core-based system-on-a-chip designs
TLDR
We define the problem of architecting voltage islands in core-based designs and present a new algorithm for simultaneous voltage island partitioning, voltage level assignment and physical-level floorplanning. Expand
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Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints
TLDR
We present a novel energy-aware scheduling (EAS) algorithm which statically schedules both communication transactions and computation tasks onto heterogeneous network-on-chip (NoC) architectures under real-time constraints. Expand
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Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
TLDR
We present an algorithm which automatically maps the IPs onto a generic regular Network on Chip (NoC) architecture and constructs a deadlock-free deterministic routing function such that the total communication energy is minimized. Expand
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Application-specific buffer space allocation for networks-on-chip router design
TLDR
We present a system-level buffer planning algorithm that can be used to customize the router design in networks-on-chip (NoCs) to match the communication pattern, such that the overall performance is maximized. Expand
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Communication and task scheduling of application-specific networks-on-chip
TLDR
The objective of the paper is to introduce a novel energy-aware scheduling (EAS) algorithm which statically schedules application-specific communication transactions and computation tasks onto heterogeneous network-on-chip architectures. Expand
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