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A 7-Round Parallel Hardware-Saving Accelerator for Gaussian and DoG Pyramid Construction Part of SIFT
TLDR
An FPGA-implementable hardware accelerator for SIFT part is presented and Stratified Gaussian Convolution scheme and 7-Round Parallel Computation scheme are introduced to reduce the hardware cost and improve process speed, meanwhile keeping high accuracy. Expand
A Foreground Extraction Algorithm Based on Adaptively Adjusted Gaussian Mixture Models
TLDR
A background subtraction method is proposed based on the popular Gaussian Mixture Models technique and a scheme is put forward to adaptively adjust the number of Gaussian distributions aiming at speeding up execution. Expand
An FPGA-Based Real-Time Hardware Accelerator for Orientation Calculation Part in SIFT
TLDR
By introducing LUT-Based Square Root Computation and Shifting-Based Orientation Calculation with use of dual-port DDR2 memory access, this paper achieves to reach real-time process speed, meanwhile keeping high accuracy. Expand
Motion Detection Based on Background Modeling and Performance Analysis for Outdoor Surveillance
TLDR
An effective scheme to improve the adaptive background model for each pixel by introducing a background training parameter into every Gaussian model, and region-based scheme is applied to judgment by utilizing both spatial and temporal information is proposed. Expand
Adaptively Adjusted Gaussian Mixture Models for Surveillance Applications
TLDR
An Adaptively Adjustment Mechanism was proposed by fully utilizing Gaussian distributions with least number so as to save the amount of computation and was able to resist illumination change in scene and remove shadows of motion. Expand
A Hardware Accelerator with Variable Pixel Representation & Skip Mode Prediction for Feature Point Detection Part of SIFT Algorithm
TLDR
This paper proposes a hardware accelerator structure of the Feature Point Detection part in SIFT which is possible to implement on FPGA and applies integer-based Variable Pixel Representation which helps to reach real-time processing. Expand
A FPGA-Based Dual-Pixel Processing Pipelined Hardware Accelerator for Feature Point Detection Part in SIFT
TLDR
An FPGA-implementable hardware accelerator for feature point detection of SIFT by introducing dual-pixel processing and the 3-stage-interpolation pipelined architecture with use of dual-port DDR2 memory access to further improve process speed and keep high accuracy. Expand
Bayesian Network based Abnormality Detection with Genetic Algorithm optimization
TLDR
A novel Bayesian Network (BN) based AD method for smart surveillance in scenes containing large scale viewpoint changes without model-relearning is proposed, which can provide more robust detection experience with retained accuracy. Expand
Robust Background Segmentation Using Background Models for Surveillance Application
TLDR
Features of intensity and texture information are utilized to eliminate the shadow of moving objects in Gaussian Mixture Models Integrated with modified Gaussian mixture models by redefining the update criterion, proposed algorithm is adapted to the flexible illumination environment. Expand
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