Learn More
Harnessing the potential of single crystal inorganic nanowires for practical advanced nanoscale applications requires not only reproducible synthesis of highly regular one-dimensional (1D) nanowire arrays directly on device platforms but also elegant device integration which retains structural integrity of the nanowires while significantly reducing or(More)
A universal compact potential model for all types of double-gate MOSFETs is presented. An analytical closed-form solution to a 2D Poisson's equation is obtained with the approximation that a vertical channel potential distribution is a cubic function of position. As a result, an analytical equation for the threshold voltage is derived from the proposed(More)
An analytical model of a nanogap-embedded field-effect transistor, which is termed here simply as a biotransistor, is developed in this study. A surface potential model is attained by solving a 2-D Poisson equation with approximation of a parabolic potential profile along the channel depth. The analytical threshold voltage is then derived from the surface(More)
A circuit element, named bistable resistor (or biristor), is proposed. The biristor has two stable resistance states. A high resistance state and low leakage current are maintained until an applied voltage reaches a latch-up voltage to trigger an avalanche effect. A low resistance state and high current are attained at voltage above the latch up. The low(More)
Silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8 nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N-and P-channel SiNAWI-FET showed the highest driving current on (110)/<110>(More)
An analytical threshold voltage model for double-gate MOSFETs with localized charges is developed. From the 2-D Poisson's equation with parabolic potential approximation, a compact threshold voltage model is derived. The proposed model is then verified with a 2-D device simulator. The model can be used to investigate hot-carrier-induced device degradation(More)
A gateless NPN Si nanowire, which has been named ‘biristor’ originating from bistable resistor, is presented for a high-density and high-speed memory with a standard CMOS technology. A hysteric I–V characteristic is utilized for the data storage, exhibiting a write and read time of less than 2nsec, a sensing current window of 0.23mA,(More)
Label-free electrical detection of avian influenza (AI) is demonstrated for the development of a point-of-care testing (POCT) platform. For a new POCT platform, a novel field effect transistor (FET)-based biosensor array was fabricated with conventional complementary metal-oxide-semiconductor (CMOS) technology. Nanogap-embedded separated double-gate FETs(More)
The body thickness dependence of impact ionization for a multiple-gate fin field-effect transistor (FinFET) is presented. It is found that the nonlocal effect and series resistance are distinct features of reduced impact ionization in the multiple-gate FinFET, and these effects become more pronounced as the body thickness decreases. The impact ionization(More)
A FinFET-based unified-RAM (URAM) using the band offset of Si/SiC is demonstrated for the fusion of a non-volatile memory (NVM) and capacitorless 1T-DRAM operation. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating body caused by the band offset are combined in a bulk FinFET to allow two memory operations in a single transistor. The device is(More)