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Charge Pump Phase locked loops are used in a variety of applications, including on chip clock synthesis, symbol timing recovery for serial data streams, and generation of frequency agile high frequency carrier signals. In many applications PLLýs are embedded into larger digital systems, in consequence, analogue test access is often limited. Test(More)
Due to a number of desirable operational and design characteristics, CP-PLL’s (Charge Pump Phase locked loops) have, in recent years become a pervasive PLL architecture. CP-PLL architectures are exploited for a variety of applications such as on chip clock generation, CRC (clock recovery circuits) and Radio frequency synthesis applications. This paper(More)
This paper describes the front-end architecture for a fully integrated low voltage CMOS video DSP function, including AGC, equalisation, clamping, sync and A/D conversion. Attention is paid to minimising the influence of substrate and power supply noise despite a large digital part with differing clock domains. The system maximises the available dynamic(More)
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