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Recent architectural advancements in reconfigurable devices have exposed the ability to support massive parallelism inside of small, low-cost, embedded devices. The massive parallelism inside of these reconfigurable devices has promised to bring an unprecedented level of performance to the embedded systems domain. However, the complexity of programming(More)
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-programmable chip (MPSoPC) architectures. As researchers are investigating new methods for migrating portions of applications into custom hardware circuits, it is also critical to(More)
As computer systems evolve towards exascale and attempt to meet new application requirements such as big data, conventional memory technologies and architectures are no longer adequate in terms of bandwidth, power, capacity, or resilience. In order to understand these problems and analyze potential solutions, an accurate simulation environment that captures(More)
—This paper introduces hthreads, a unifying programming model for specifying application threads running within a hybrid computer processing unit (CPU)/field-programmable gate-array (FPGA) system. Presently accepted hybrid CPU/FPGA computational models—and access to these computational models via high level languages—focus on programming language extensions(More)
In this paper, we present hthreads, a unifying programming model for specifying application threads running within a hybrid CPU/FPGA system. Threads are specified from a single pthreads multithreaded application program and compiled to run on the CPU or synthesized to run on the FPGA. The hthreads system, in general, is unique within the reconfigurable(More)
The paper presents the new hardware thread interface (HWTI), a meaningful and semantic rich target for a high level language to hardware descriptive language translator. The HWTI provides a hardware thread with the same thread system calls available to software threads, a fast global distributed memory, support for pointers, a generalized function call(More)
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop new high-level programming models , and not just focus on extensions to programming languages, for enabling accessibility and portability of standard high level applications across(More)
The hthreads group is developing the hybridthreads compiler (HTC) to satisfy the need for a C compiler that can generate hardware threads. Compiling C-like languages to hardware has been studied a number of times. The goal of past projects is different than the goal of HTC because past projects focused on creating and optimizing hardware based co-processors(More)
Thanks to advancements in fabrication techniques, it will soon be possible to place 10's if not 100's of cores on a single hybrid CPU/FPGA reconfigurable chip. This has lead to a new field of study, namely Multi-Core Systems on a Programmable Chip (MCSoPC). The problems being studied with MCSoPC are not unlike the problems studied 20 years ago when multiple(More)
In this paper, we present a novel memory system checkpointing method that very efficiently stores the complete memory state at a given instant in time to a SSD. Our design relies on a modified memory controller that can issue commands directly to the SSD without relying on system software support and SSD controller firmware that is aware of the checkpoint(More)