• Citations Per Year
Learn More
Leakage is one of today's most important VLSI design issues, and ASIC design tools require accurate library leakage models. Leakage models have been traditionally derived from Spice simulation, but this approach is difficult and inflexible. Further, Spice simulation may not be possible for all IP in the library. We propose a new approach to modeling leakage(More)
  • 1