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A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology
This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both theExpand
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A Circuit for Reducing Large Transient Current Effects on Processor Power Grids
A circuit that reduces power supply transients by controlling the frequency ramp between the initial and final operating frequencies of a microprocessor is presented. This is accomplished byExpand
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ST-MRAM Fundamentals, Challenges, and Outlook
Magnetoresistive Random Access Memory (MRAM) technology was introduced into the market last decade in the form of Toggle MRAM, available in densities up to 16Mb. In the last few years, Spin-TorqueExpand
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A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology
This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both theExpand
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A new test and characterization scheme for 10+ GHz low jitter wide band PLL
This paper presents a new test and characterization scheme for 10+ GHz low jitter wide band PLL in 90 nm partially depleted (PD) silicon-on-insulator (SOI) CMOS technology. We measure the frequencyExpand
Electroluminescence from novel porous silicon p-n junction devices
The electroluminescent properties of various porous silicon pn junction devices have been investigated. Devices were fabricated by constant current anodization method as well as a novel methodExpand
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