Jieming Qi

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This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both the receiver and the transmitter use dynamic adaptation to combat parameter drift due to changing supply and temperature. A 3-tap FFE is included in the(More)
This paper presents a new test and characterization scheme for 10+ GHz low jitter wide band PLL in 90 nm partially depleted (PD) Silicon-On-Insulator (SOI) CMOS technology. We measure the frequency range of VCOs without adding any devices for test between charge-pump (CP) and voltage- controlled oscillator (VCO). That test scheme gives us the intermediate(More)
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