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In this paper we describe a VLSI system architecture for high-speed synthesis of 3D images composed of diffusely reflective surfaces. The system consists of two loosely coupled sub-systems. The first sub-system computes the form-factor matrixF. The form-factors are computed by an efficient ray-tracing algorithm. The second sub-system, a multiprocessor(More)
As there are unbalanced communications between each computing core in multi-core system, a dynamic weight arbiter for networks-on-chip is designed and implemented in this paper. This arbiter uses a simple method to realize static arbitration mechanism based on Lottery algorithm, and on this basis, according to the congestion situation detected in all(More)
A buffer allocation algorithm based on self-similar queuing model is proposed, with the consideration of self-similar communication characteristics of Networks-on-Chip and virtual-channels. It calculates the overflow probability of each virtual-channel according the Discrete Poisson Pareto Burst Process (DPPBP) model, which is the basis of distributing(More)
Reconfigurable computing system is usually composed of general-purpose processors and reconfigurable coprocessors, featuring the flexibility of general-purpose processors and high computation performance. It is hard for traditional reconfigurable computing system to get balance between the utilization ratios of reconfigurable coprocessor and the complete(More)
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