Jiao-jiao Zhu

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For accurate prediction of via yield, via chains are usually fabricated on test chips to investigate issues about vias. To minimize the randomness of experiments and make the testing results more convincing, the confidence level and estimation precision of the via failure rate are investigated in this paper. Based on the Poisson yield model, the method of(More)
Due to the importance of metal layers in the product yield, serpentine test structures are usually fabricated on test chips to extract parameters for yield prediction. In this paper, the confidence level and estimation precision of the average defect density on metal layers are investigated to minimize the randomness of experimental results and make the(More)
In existing integrated circuit (IC) fabrication methods, the yield is typically limited by defects generated in the manufacturing process. In fact, the yield often shows a good correlation with the type and density of the defect. As a result, an accurate defect limited yield model is essential for accurate correlation analysis and yield prediction. Since(More)
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