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Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless scaling, if uncompensated, degrades the performance and signal integrity of on-chip metal interconnects. These systems have therefore become increasingly communications-limited. The(More)
Main-stream general-purpose microprocessors require a collection of high-performance interconnects to supply the necessary data movement. The trend of continued increase in core count has prompted designs of packet-switched network as a scalable solution for future-generation chips. However, the cost of scalability can be significant and especially hard to(More)
As microprocessor chips integrate a growing number of cores, the issue of interconnection becomes more important for overall system performance and efficiency. Compared to traditional distributed shared-memory architecture, chip-multiprocessors offer a different set of design constraints and opportunities. As a result, a conventional packet-relay(More)
This paper analyzes the power consumption of an RFID tag and presents a new architecture of a low-power baseband-processor for this special passive tag. The tag consists of a power reception system, an emitter/receiver analog module, an EEPROM and a low-power baseband-processor, compatible with the newest EPCtrade C1G2 UHF RFID protocol. Meanwhile some(More)
Ultrafast pulse generation and detection are pivotal functions in ultra-wideband (UWB) impulse radios. This paper shows that digitally-assisted distributed circuit techniques provide an energy-efficient, reconfigurable solution for both functions, as demonstrated in two new circuits: a pulse generator that can generate reconfigurable pulse waveforms with(More)
We present a wideband resistive feedback CMOS low-noise amplifier (LNA) with noise cancellation technique for ultra-wideband applications. The LNA achieves a 3-dB bandwidth of 0.7-6.5 GHz, power gain of 12.5 dB, and noise figure of 3.5-4.2 dB within the 3-dB bandwidth. The input matching is better than -11 dB from 0.7 to 12 GHz. The IIP3 is measured -5 dBm(More)
With increasing core count, chip multiprocessors (CMP) require a high-performance interconnect fabric that is energy-efficient. Well-engineered transmission line-based communication systems offer an attractive solution, especially for CMPs with a moderate number of cores. While transmission lines have been used in a wide variety of purposes, there lack(More)
This paper presents the first chip-scale demonstration of an intra-chip free-space optical interconnect (FSOI) we recently proposed. This interconnect system provides point-to-point free-space optical links between any two communication nodes, and hence constructs an all-to-all intra-chip communication fabric, which can be extended for inter-chip(More)
The growing number of cores in chip multiprocessors increases the importance of interconnection for overall system performance and energy efficiency. Compared to traditional distributed shared-memory architectures, chipmultiprocessors offer a different set of design constraints and opportunities. As a result, a conventional packet-relay multiprocessor(More)
In this paper, we present a fully-integrated impulse radio UWB transmitter based on a newly-developed ultrafast pulse circuit technique, distributed waveform generator (DWG). A DWG time-interleaves multiple digital pulse generators, and then combines all generated pulses using a wideband on-chip transmission line. A DWG is low power and fully reconfigurable(More)