Learn More
Bitstream parsing is a basic task in video decoding systems. With the development of video compression standards, the trend of the VLSI architecture for bitstream parser is toward programmable. Due to the strong data-dependency and bit-level sequential operations, bitstream parsing is unsuitable to accelerate by general architectures, such as RISC, SIMD and(More)
This paper proposes an efficient SIMD architecture with parallel memory for 2D cosine transforms of multiple video standards. A novel parallel memory scheme is employed to provide conflict-free parallel access in both horizontal and vertical directions with the successive or even/odd mode, as well as to eliminate data permutation and matrix transposition.(More)
  • 1