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This paper introduces the architecture of an AVS (audio video coding standard working group of China) hardware decoding system. The system includes system layer decoding, video decoding and audio decoding. It supports 720p/1080i HD (high-definition) format real-time decoding. A VLSI chip is designed by using this architecture.
Quantum-dot cellular automata (QCA) has been advocated as a promising emerging nanotechnology for designing future nanocomputing systems. However, at device level, the large number of expected defects represents a significant hurdle for reliable computation in QCA-based systems. In this paper, we present an information-theoretic approach to investigate the(More)
Write-through policy employed in many high-performance microprocessors provides good tolerance to soft errors in cache systems. However, it also incurs large energy overhead due to the increased accesses to caches at the lower level (e.g., the L2 cache) during write operations. In this paper, we propose a new cache architecture referred to as <i>way-tagged(More)
Molecular electronics such as silicon nanowires (NW) and carbon nanotubes (NT) are considered to be the fabric of next generation nanocomputing. However, the excessive defects caused by bottom-up self-assembly fabrication have become a fundamental obstacle for achieving reliable computation in molecular systems. In this paper, we present an(More)
Power consumption poses one of the fundamental barriers for deploying mobile computing devices in energy-constrained situations with varying operation conditions. In particular, leakage power is projected to increase exponentially in future semiconductor process nodes. This challenging problem is pressing for renewed focus on power-performance optimization(More)