Jianping Quan

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Researches on DPA-resistant ECC implementation are concentrated in algorithm level. All these countermeasures need a big random number and extra memory overhead which are rare resources in hardware. On the other hand, universal countermeasures in logic level have a big area overhead and face many popular DPA attacks. To avoid these disadvantages, we attempt(More)
Recently DPA resistant logic styles are of great concern. As far as we know, each kind of logic style has its own drawbacks. Masking logic styles can easily be attacked by the template attack. For dual-rail logic styles, TDPL can only keep the total power consumption of the whole cycle constant; as for WDDL, it becomes more and more difficult to efficiently(More)
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