Jianing Su

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In this paper, a low-cost VLSI implementation of a pipeline fast Fourier transform (FFT) processor capable of supporting from 1k to 32k FFT sizes is presented. The radix-2<sup>2</sup>/2<sup>3</sup> based pipeline structure reduces the steps of normal complex multiplications, and the single-path delay feedback (SDF) memory access method ensures a minimum(More)
A DVB-C/ITU J.83-A compliant QAM (Quadrature Amplitude Modulation) demodulator suitable for digital cable TV is proposed, which can support 4~256QAM with variable bit rate up to 80Mbps. It integrates a 10-bit 40MSPS ADC, (204,188) Reed-Solomon decoder as well as a convolutional interleaver. The chip is implemented in SMIC 0.25um CMOS technology with die(More)
In this paper, a low cost VLSI implementation of an LDPC decoder for the Advanced Broadcasting System of Satellite (ABS-S) is presented. The decoder is fully compatible with all the 8 code rates in ABS-S standard. The layered decoding with sorted scheduling architecture is employed and the scaled min-sum belief propagation method is used for check node(More)
The Ziggurat algorithm is an efficient way for building a Gaussian random number generator (GRNG), which is useful in many scientific and engineering applications. As the classic ziggurat-based GRNG includes nonlinear operations in judging the wedge and tail regions, which is complicated and resource consuming. An improved ziggurat algorithm is proposed by(More)
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