Jianchao Lu

Learn More
A novel clock mesh network synthesis approach is proposed in this paper which generates an improved mesh size with registers placed incrementally considering the timing slack on the data paths and the non-uniform grid wire placement. The primary objective of the method is to reduce the power dissipation without a global skew degradation, which is achieved(More)
A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path in(More)
A clock polarity assignment method is proposed that reduces the peak current on the vdd/gnd rails of an integrated circuit. The impacts of (i) the output capacitive load on the peak current drawn by the sink-level clock buffers, and (ii) the buffer/inverter replacement scheme of polarity assignment on timing accuracy are considered in the formulation. The(More)