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Magnetic random access memory (MRAM) is a promising memory technology, which has fast read access, high density, and non-volatility. Using 3D heterogeneous integrations, it becomes feasible and cost-efficient to stack MRAM atop conventional chip multiprocessors (CMPs). However, one disadvantage of MRAM is its long write latency and its high write energy. In(More)
Coca-Cola (Coke) and Pepsi are nearly identical in chemical composition, yet humans routinely display strong subjective preferences for one or the other. This simple observation raises the important question of how cultural messages combine with content to shape our perceptions; even to the point of modifying behavioral preferences for a primary reward like(More)
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single application is critical in light of the expanding performance demands of important future workloads. This work addresses the problem of dynamically optimizing power consumption of(More)
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially in the context of chip multiprocessors (CMPs), present many challenges in area requirements, core-to-cache balance, power consumption, and design complexity. New advancements in(More)
In this paper we investigate the problem of uneven energy consumptions in a large class of many-to-one sensor networks. In a many-to-one sensor network, all sensor nodes generate constant bit rate (CBR) data and send them to a single sink via multihop transmissions. This type of sensor networks has many potential applications such as environmental(More)
Ranking is a fundamental operation in data analysis and decision support and plays an even more crucial role if the dataset being explored exhibits uncertainty. This has led to much work in understanding how to rank the tuples in a probabilistic dataset in recent years. In this article, we present a unified approach to ranking and top-k query processing in(More)
The PERCS system was designed by IBM in response to a DARPA challenge that called for a high-productivity high-performance computing system. A major innovation in the PERCS design is the network that is built using Hub chips that are integrated into the compute nodes. Each Hub chip is about 580 mm in size, has over 3700 signal I/Os, and is packaged in a(More)
In a many-to-one sensor network, all sensor nodes generate CBR data and send them to a single sink via multihop transmissions. Sensor nodes sitting around the sink need to relay more traffic and suffer much faster energy consumption rates (ECR), and thus have much shorter expected lifetime. This may result in severe consequences such as early dysfunction of(More)
Software product line (SPL) engineering is a software engineering approach to building configurable software systems. SPLs commonly use a feature model to capture and document the commonalities and variabilities of the underlying software system. A key challenge when using a feature model to derive a new SPL configuration is determining how to find an(More)