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Character projection is a key technology to enhance throughput of e-beam lithography, in which characters need to be selected and placed on the stencil. This paper solves the problem of planning for overlapping-aware row-structure stencil, and also considers multi-column cell system for further throughput improvement. We propose an integrated framework to(More)
E-Beam Lithography (EBL) is a maskless nanolithography technology that creates features on a wafer by directly shooting a beam of electrons onto the wafer. Different from the current mainstream optical lithography technology, <i>i.e</i>. 193nm ArF immersion lithography, EBL overcomes the limit of light diffraction. As one of the most promising next(More)
Triple Patterning Lithography (TPL) is widely recognized as a promising solution for 14/10nm technology node. In this paper, we propose an efficient layout decomposition approach for TPL, with the objective to minimize the number of conflicts and stitches. Based on our analysis of actual benchmarks, we found that the whole layout can be reduced into several(More)
Triple Patterning Lithography (TPL) is regarded as a promising technique to handle the manufacturing challenges in 14nm and beyond technology node. It is necessary to consider TPL in early design stages to make the layout more TPL friendly and reduce the manufacturing cost. In this paper, we propose a flow to co-optimize cell layout decomposition and(More)
Due to a significant mismatch between the objectives of wirelength and routing congestion, the routability issue is becoming more and more important in VLSI design. In this paper, we present a high quality placer Ripple 2.0 to solve the routability-driven placement problem. We will study how to make use of the routing path information in cell spreading and(More)
Modern placement process involves global placement, legalization, and detailed placement. Global placement produce a placement solution with minimized target objective, which is usually wire-length, routability, timing, etc. Legalization removes cell overlap and aligns the cells to the placement sites. Detailed placement further improves the solution by(More)
To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous works either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying certain density uniformity constraint. However, due to more stringent manufacturing challenges, more criteria, like(More)