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—In this paper, two high-speed and low-power I/O circuits are developed using through-silicon-interposer (TSI) for 2.5D integration of multi-core processor and memory in 65nm CMOS process. For a 3mm TSI interconnection of transmission line (T-line), the first I/O circuit is a low-voltage-differential-signal (LVDS) buffer and the second one is a(More)
This paper proposes a novel architecture for plug-in electric vehicles (PEVs) dc charging station at the megawatt level, through the use of a grid-tied neutral point clamped (NPC) converter. The proposed bipolar dc structure reduces the step-down effort on the dc–dc fast chargers. In addition, this paper proposes a balancing mechanism that allows handling(More)
A linearity improvement technique is proposed on the design of low frequency (132 KHz center frequency, 40 KHz band frequency) power-line communication band-pass filter, which focus on the linearity of large R-MOSFET. In order to enhance the linearity of the triode-mode MOSFET variable resistors, driving the controlling voltages of the RMOSFET in a resistor(More)
This paper presents a new time-mode duty-cycle-modulation-based high accuracy temperature sensor. Different from the well-known ΣΔADC based read-out structure, this temperature sensor's architecture utilizes a temperature-dependent oscillator to convert the temperature information into temperature related time-mode parameter, which means that(More)