Jiacheng Wang

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In this paper, two high-speed and low-power I/O circuits are developed using through-silicon-interposer (TSI) for 2.5D integration of multi-core processor and memory in 65nm CMOS process. For a 3mm TSI interconnection of transmission line (T-line), the first I/O circuit is a low-voltage-differentialsignal (LVDS) buffer and the second one is a(More)
Multilevel voltage-source converter topologies are widely used today in high-power applications such as mediumvoltage drives. On the other hand, studies on matrix converters (MCs) have been mainly limited to the low power range. With the intention to combine benefits from both multilevel structure and direct power conversion, this paper investigates the(More)
This paper proposes a novel architecture for plug-in electric vehicles (PEVs) dc charging station at the megawatt level, through the use of a grid-tied neutral point clamped (NPC) converter. The proposed bipolar dc structure reduces the step-down effort on the dc–dc fast chargers. In addition, this paper proposes a balancing mechanism that allows handling(More)
This paper presents a low-power on-chip RC oscillator with compensation for temperature and supply voltage variation. This circuit is based on a conventional on-chip oscillator, with only a capacitor and a comparator to avoid mismatch. Multiple current sources flow through the same resistor to generate a reference voltage. This is complemented with the(More)