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27.4 An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics GDDR4 DRAM has a source-synchronous clocking scheme, which DRAM with Low-Power and Low-Noise Data-Bus has the benefit ofjitter tolerance, however, when there is duty-cycle distortion in clock, timing margin is reduced by twice the amount of Inversion the duty-cycle distortion. The duty-cycle distortion is(More)
A novel high-speed and low-voltage CMOS level shifter circuit is proposed. The proposed circuit is suitable for block-level dynamic voltage and frequency scaling (DVFS) environment or multiple-clock and multiple-power-domain logic blocks. In order to achieve high performance in a chip consisting of logic blocks having different VDD voltages, the proposed(More)
Increasing frequency and reducing time margin have made designs of power delivery networks (PDNs) on board to be an integral part of chip designs. Power delivery network designs are usually achieved by mounting the decoupling capacitors on power plates so that the designed power impedance is relatively lower on the interested frequency ranges. But, some(More)
Recent years, various percutaneous procedures including cervical nucleoplasty have been developed for disc decompressions to relieve radicular pains caused by disc herniations. We report the application of percutaneous cervical nucleoplasty (PCN) by using the navigable disc decompression device in two patients of cervical herniated intervertebral discs(More)
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