Jesús de la Cruz Alejo

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This paper presents a technique to solve mismatch compensation problems in current mirrors using the floating gate MOS transistor. To reduce mismatches, the tunneling and injection processes are applied in a 1.2µm CMOS process. It takes into account the long-term voltage storage as charge on the floating gate of a transistor pMOS. Experimental(More)
This work presents an optimized Implementation on Field Programmable Gate Array (FPGA) Architecture for an Infomax algorithm based on Independent Component Analysis (ICA). We use this algorithm to solving Blind Source Separation (BSS) problems in real-time mixed signal processing in order to clean speech signals under noisy environments and to probe the(More)
This paper presents a four-quadrant analog multiplier. The architecture of the multiplier is designed with floating-gate CMOS transistors formed by squaring and current mirrors circuits. The results shown are accurate and appropriate. It is based on the square-law dependence of the MOS-transistor drain current on the gate-to-source voltage. To demonstrate(More)
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