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This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG(More)
ÐThe paper presents a new fault diagnosis technique for scan-based designs with BIST. It can be used for nonadaptive identification of the scan cells that are driven by erroneous signals. The proposed scheme employs a pseudorandom scan cell selection routine which, in conjunction with a conventional signature analysis and simple reasoning procedure, allows(More)
The paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces significantly switching rates in scan chains with minimal hardware modification. Experimental results obtained for industrial circuits clearly indicate that switching activity can be reduced up to 150 times along with improved compression(More)
This paper presents a novel methodology of designing generators and compactors of test data. The essence of the proposed approach is to use a set of transformations, which alters the structure of the conventional linear feedback shift registers (LFSRs) while preserving the transition function of the original circuits. It is shown that after applying the(More)