Abs t rac t . We describe a technique for verifying the control logic of pipelined microprocessors. It handles more complicated designs, and requires less human intervention, than existing methods.â€¦ (More)

Many different methods have been devised for automatically verifying finite state systems by examining state-graph models of system behavior. These methods all depend on decision procedures thatâ€¦ (More)

The temporal logic model checking algorithm developed by Clarke, Emerson, and Sistla [9] is modified to represent a state graph using binary decision diagrams (BDD's) [4]. Because this representationâ€¦ (More)

The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDDâ€™s) [7] and partitioned trunsirion relationsâ€¦ (More)

Burch and Dill [3] described an automatic method for verifying a pipelined processor against its instruction set architecture (ISA). We describe three techniques for improving this method. We showâ€¦ (More)

We significantly reduce the complexity of BDD-based symbolic verification by using partitioned transition relations to represent state transition graphs. On an example pipeline circuit, thisâ€¦ (More)

Combinational verification is an important piece of most equivalence checking tools. In the recent past, many combinational verification algorithms have appeared in the literature. Previous resultsâ€¦ (More)

We describe an efficient validity checker for the quantifier-free logic of equality with uninterpreted functions. This logic is well suited for verifying microprocessor control circuitry since itâ€¦ (More)