Jerry J. Cupal

Learn More
This paper describes a one-credit laboratory course for freshmen majoring in electrical and computer engineering (ECE). The course is motivational in nature and exposes the students to a wide range of areas of electrical and computer engineering. The authors believe it is important to give freshmen a broad perspective of what ECE is all about, and to shine(More)
We show transformations that convert blocking assignments into non-blocking assignments. Such transformations are useful because the parallel-processing nature of hardware is more easily conceptualized and mapped to technology with non-blocking assignment. To validate our theory, we synthesized using Synopsys FPGA Express, which supports both blocking and(More)
It is dr;fficult to develop pure behavioral Verilog models of synchronous digital systems (such as a CISC microprocessor) that produce accurate timing information using only the built-in reg declaration and blocking assignment statements. We present a novel behavioral module definition that can be instantiated instead of a reg to abstractly model(More)