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A number of studies have shown that increased APP levels, resulting from either a genomic locus duplication or alteration in APP regulatory sequences, can lead to development of early-onset dementias, including Alzheimer's disease (AD). Therefore, understanding how APP levels are regulated could provide valuable insight into the genetic basis of AD and(More)
Traditionally, the only standard method of testing that has consistently provided high fault coverage has been scan test due to the high controllability and high observability this technique provides. The scan chains used in scan test not only allow test engineers to control and observe a chip, but these properties also allow the scan architecture to be(More)
Transgenic models of Alzheimer's disease (AD) have made significant contributions to our understanding of AD pathogenesis, and are useful tools in the development of potential therapeutics. The fruit fly, Drosophila melanogaster, provides a genetically tractable, powerful system to study the biochemical, genetic, environmental, and behavioral aspects of(More)
BACKGROUND A central event in Alzheimer's disease (AD) is the regulated intramembraneous proteolysis of the beta-amyloid precursor protein (APP), to generate the beta-amyloid (Abeta) peptide and the APP intracellular domain (AICD). Abeta is the major component of amyloid plaques and AICD displays transcriptional activation properties. We have taken(More)
Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shipped to the customers fault-free. However, at-speed tests have been known to create higher-than-average switching activity, which normally is not accounted for in the design of the(More)
— As technology scales, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise plays a greater role in sub-100nm technologies and creates signal integrity issues in the chip. It is vital to consider supply voltage noise effects (i) during design validation to apply(More)
The objective of this preliminary study is to investigate whether educational video games can be integrated into a classroom with positive effects for the teacher and students. The challenges faced when introducing a video game into a classroom are twofold: overcoming the notion that a "toy" does not belong in the school and developing software that has(More)
— Scan designs used for testing also provide an easily accessible port for hacking. In this paper, we present a new low-cost secure scan design that is effective against scan-based side-channel attacks. By integrating a test key into test vectors that are scanned into the chip, testing and accessing scan chains are guaranteed to be allowed only by an(More)
The limitations of pattern generation tools are beginning to surface as parasitic coupling capacitance in high speed interconnects only worsens as the industry approaches sub-50nm technologies. This can create a gap between the delay experienced on critical and long paths during test and the delay of the same paths in the field. In this paper, we propose a(More)