Learn More
—A 128-bit, 1.6 pJ/bit, 96% stable chip ID generation circuit utilizing process variations is designed in a 0.13 m CMOS process. The circuit consumes 162 nW from a 1 V supply at low readout frequencies and 1.6 W at 1 Mb/s. Cross-coupled logic gates were employed to simultaneously generate, amplify, and digitize the random circuit offset to create a stable(More)
Advances in electronic-neural interfaces have shown great potential for both neuroscience research and medical devices. Much of the work to date has focused on short-range inductive links for power and communication transfer [1]. There is an emerging need for active miniaturized systems that stream neural data in the far field, which would enable the(More)
In this paper we present a pre-amplifier designed for neural recording applications. Extremely low power dissipation is achieved by operating in an open-loop configuration, restricting the circuit to a single current branch, and reusing current to improve noise performance. Our amplifier exhibits 3.5 microVrms of input-referred noise and has a(More)
Many integrated circuit applications require a unique identification number (ID) on each die that can be read anytime during the lifetime of the chip. A robust read-only ID is important for labeling RFID tags, addressing low-power wireless sensor nodes, IC process quality control, and secure documentation. Traditional methods of writing addresses into ROMs(More)
— This paper presents two novel hardware random number generators (RNGs) based on latch metastability. We designed the first, the DC-nulling RNG, for extremely low power operation. The second, the FIR-based RNG, uses a predictive whitening filter to remove non-random components from the generated bit sequence. In both designs, the use of floating-gate(More)
Rapid development in miniature implantable electronics are expediting advances in neuroscience by allowing observation and control of neural activities. The first stage of an implantable biosignal recording system, a low-noise biopotential amplifier (BPA), is critical to the overall power and noise performance of the system. In order to integrate a large(More)
We have a developed an analog VLSI system that models the coordination of neurobiological segmental oscillators. We have implemented and tested a system that consists of a chain of eleven pattern generating circuits that are synaptically coupled to their nearest neighbors. Each pattern generating circuit is implemented with two silicon Morris-Lecar neurons(More)
— We present the NeuralWISP, a wireless neural interface operating from harvested RF energy. The NeuralWISP is compatible with commercial RFID readers and operates at a range up to 1m. It includes a custom low-noise, low power amplifier IC for processing the neural signal and an analog spike detection circuit for reducing digital computational requirements(More)
We present the NeuralWISP, a wireless neural interface operating from far-field radio-frequency RF energy. The NeuralWISP is compatible with commercial RF identification readers and operates at a range up to 1 m. It includes a custom low-noise, low-power amplifier integrated circuit for processing the neural signal and an analog spike detection circuit for(More)
Direct processing of raw high-dimensional data such as images and video by machine learning systems is impractical both due to prohibitive power consumption and the " curse of dimensionality, " which makes learning tasks exponentially more difficult as dimension increases. Deep machine learning (DML) mimics the hierarchical presentation of information in(More)