Jeremy Holleman

Learn More
A 128-bit, 1.6 pJ/bit, 96% stable chip ID generation circuit utilizing process variations is designed in a 0.13 m CMOS process. The circuit consumes 162 nW from a 1 V supply at low readout frequencies and 1.6 W at 1 Mb/s. Cross-coupled logic gates were employed to simultaneously generate, amplify, and digitize the random circuit offset to create a stable(More)
Advances in electronic-neural interfaces have shown great potential for both neuroscience research and medical devices. Much of the work to date has focused on short-range inductive links for power and communication transfer [1]. There is an emerging need for active miniaturized systems that stream neural data in the far field, which would enable the(More)
This paper presents two novel hardware random number generators (RNGs) based on latch metastability. We designed the first, the DC-nulling RNG, for extremely low power operation. The second, the FIR-based RNG, uses a predictive whitening filter to remove nonrandom components from the generated bit sequence. In both designs, the use of floating-gate memory(More)
Rapid development in miniature implantable electronics are expediting advances in neuroscience by allowing observation and control of neural activities. The first stage of an implantable biosignal recording system, a low-noise biopotential amplifier (BPA), is critical to the overall power and noise performance of the system. In order to integrate a large(More)
An analog implementation of a deep machinelearning system for efficient feature extraction is presented in this work. It features online unsupervised trainability and non-volatile floating-gate analog storage. It utilizes a massively parallel reconfigurable current-mode analog architecture to realize efficient computation, and leverages algorithm-level(More)
In this paper we present a pre-amplifier designed for neural recording applications. Extremely low power dissipation is achieved by operating in an open-loop configuration, restricting the circuit to a single current branch, and reusing current to improve noise performance. Our amplifier exhibits 3.5 microVrms of input-referred noise and has a(More)
We present the NeuralWISP, a wireless neural interface operating from far-field radio-frequency RF energy. The NeuralWISP is compatible with commercial RF identification readers and operates at a range up to 1 m. It includes a custom low-noise, low-power amplifier integrated circuit for processing the neural signal and an analog spike detection circuit for(More)
A floating-gate current-output analog memory is implemented in a 0.13-μm digital CMOS process. The proposed memory cell achieves random-accessible and bidirectional updates with a sigmoid update rule. A novel writing scheme is proposed to obtain tunneling selectivity without on-chip highvoltage switches or charge pumps, and reduces interconnections and pin(More)
ELECT An ultra-low-power tunable bump circuit is presented. It incorporates a novel wide-input-range tunable pseudo-differential transconductor linearised using the drain resistances of saturated transistors. Measurement results show that the transconductor has a 5 V differential input range with <20% of linearity error. The bump circuit demonstrates(More)