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Most previous work about the hardware design of a fuzzy logic controller (FLC) intended to either improve its inference performance for real-time applications or to reduce its hardware cost. To our knowledge, there has been no attempt to design a hardware FLC that can perform an adaptive fuzzy inference for the applications of on-line adaptation. The(More)
Due to the temporal and spatial correlation of the image sequence, the motion vector of a block is highly related to the motion vectors of its adjacent blocks in the same image frame. If we can obtain useful and enough information from the adjacent motion vectors, the total number of search points used to find the motion vector of the block may be reduced(More)
As a basic block of a multi-switching-and-processing system, fast and fair arbiters are critical to the efficiency of multi-core computing units, high-speed crossbar switches and routers, which are the key to the performance of on-chip networking/computing in a SoC and NoC. In this paper, a High-Speed and Decentralized Round-robin Arbiter (HDRA) is(More)
In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has(More)
In this paper, a fast and memory-efficient diagnostic fault simulator for sequential circuits is proposed. In it, a two-level optimization technique is developed and used to prompt the processing speed. In the first high level, an efficient list, which stores the indistinguishable faults so far for each fault during simulation, and the list maintaining(More)
In this paper, we propose a novel reconfigurable computation unit (RCU) that is higher flexible and more compact than the traditional arithmetic units. The RCU can support 22 kinds of functions. It has the ability to handle 8-bit, 16-bit and 32-bit arithmetic operations to execute the full or partial data flows of DSP applications. The proposed(More)
This paper describes an online lossless datacompression method using adaptive arithmetic coding. To achieve good compression efficiency, we employ an adaptive fuzzy-tuning modeler that applies fuzzy inference to deal efficiently with the problem of conditional probability estimation. In comparison with other lossless coding schemes, the compression results(More)
In this paper, a methodology based on a mix-mode interconnection architecture is proposed for constructing an application specific network on chip to minimize the total communication time. The proposed architecture uses a globally asynchronous communication network and a locally synchronous bus (or cross-bar or multistage interconnection network MIN).(More)