Jeonghee Shin

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Microarchitectural redundancy has been proposed as a means of improving chip lifetime reliability. It is typically used in a reactive way, allowing chips to maintain operability in the presence of failures by detecting and isolating, correcting, and/or replacing components on a first-come, first-served basis only after they become faulty. In this paper, we(More)
This paper tackles the issue of modeling chip lifetime reliability at the architecture level. We propose a new and robust structure-aware lifetime reliability model at the architecture-level, where devices only vulnerable to failure mechanisms and the effective stress condition of these devices are taken into account for the failure rate of(More)
PURPOSE This study aimed to evaluate the correlation, according to postnatal age, between plasma B-type natriuretic peptide (BNP) levels and echocardiographic parameters for the assessment of patent ductus arteriosus (PDA) in preterm infants with respiratory distress. METHODS We enrolled 42 preterm infants with respiratory distress who underwent serial(More)
Heated, humidified, high-flow nasal cannula (HHFNC) is frequently used as a noninvasive respiratory support for preterm infants with respiratory distress. But there are limited studies that compares HHFNC with nasal continuous positive airway pressure (nCPAP) only as the initial treatment of respiratory distress in preterm infants immediately after birth.(More)
Survival of very-low-birth-weight infants (VLBWI) depends on professional perinatal management that begins at delivery. Korean Neonatal Network data on neonatal resuscitation management and initial care of VLBWI of less than 33 weeks gestation born from January 2013 to June 2014 were reviewed to investigate the current practice of neonatal resuscitation in(More)
Modern processor systems are equipped with on-chip or on-board power controllers. In this paper, we examine the challenges and pitfalls in architecting such dynamic power management control systems. A key question that we pose is: How to ensure that such managed systems are "energy-secure" and how to pursue pre-silicon modeling to ensure such security? In(More)
This paper provides: 1) a very brief motivation and technological trend data to show why hard and soft errors are expected to be of increasing concern in the future; 2) a summary review of chip-level error tolerance practices today-with a brief reference to IBM's POWER6 and POWER7 designs; 3) open research challenges and current solution approaches of(More)
Next generation system designs are challenged by multiple "walls": among them, the inter-related impediments offered by power dissipation limits and reliability are particularly difficult ones that all current chip/system design teams are grappling with. In this paper, we first describe the attendant challenges in integrated (multi-dimensional) pre-silicon(More)