Jeong-A. Lee

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As the process technology scales down, interconnects become the performance bottleneck when designing multi-core processors. 3D IC can be a good solution for reducing the interconnection delay in the multi-core processors by stacking multiple layers connected through TSVs. However, 3D technology magnifies the thermal challenges in 3D multi-core processors.(More)
The performance of existing adders varies widely in their speed and area requirements, which in turn sometimes makes designers pay a high cost in area especially when the delay requirements exceeds the fastest speed of a specific adder, no matter how small the difference is. To expand the design space and manage delay/area tradeoffs, we propose new adder(More)