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A successive approximation analog-to-digital converter (ADC) is presented operating at ultra low supply voltages. The circuit is realized in a 0.18µm CMOS technology. Neither low-V T devices nor voltage boosting techniques are used. All voltage levels are between supply voltage (VDD) and ground (VSS). A passive sample-and-hold stage and an capacitor-based(More)
In this paper, a 12 bit Successive Approximation Analog to Digital Converter has been designed which has high resolution, less power consumption and medium speed. The circuit has been designed and simulated on Cadence tool in 0. 35µm AMS technology with a supply voltage of 3. 3V. Different ADC architectures are present but this SAR ADC has a salient feature(More)
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