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Electromigration due to insufficient wire width can cause the premature failure of a circuit. The ongoing reduction of circuit feature sizes has aggravated the problem over the last couple of years, especially with analog circuits. It is therefore an important reliability issue to consider current densities already in the physical design stage. We present a(More)
Interconnect with an insufficient width may be subject to electromigration and eventually cause the failure of the circuit at any time during its lifetime. This problem has gotten worse over the last couple of years due to the ongoing reduction of circuit feature sizes. For this reason, it is becoming crucial to address the problems of current densities and(More)
— Layout design of analog integrated circuits suffers from a lack of automation due to the multitude of complex design constraints. Most of them are specified and considered manually by expert designers (expert knowledge). We present a new methodology that enables the automatic inclusion of expert knowledge in the form of layout constraints. The resulting(More)
—Despite numerous advantages of three-dimensional (3D) ICs, their commercial success remains limited. In part, this is due to the wide availability of trustworthy intellectual property (IP) blocks developed for 2D ICs and proven through repeated use. Block-based design reuse is imperative for heterogeneous 3D ICs where memory, logic, analog and(More)
The island model genetic algorithm shows promise as a superior formulation based on considerations from theories of natural evolution and from the efficiencies of coarse-grained parallel computer architectures. The theory of punctuated equilibria calls for the population to be partitioned into several distinct subpopulations. These subpopulations have(More)
A new genetic algorithm for channel routing in the physical design process of VLSI circuits is presented. The algorithm is based on a problem speciic representation scheme and problem speciic genetic operators. The genetic encoding and our genetic operators are described in detail. The performance of the algorithm is tested on diierent benchmarks and it is(More)
— This paper presents a novel approach to solve the VLSI (very large scale integration) channel and switchbox routing problems. The approach is based on a parallel genetic algorithm (PGA) that runs on a distributed network of workstations. The algorithm optimizes both physical constraints (length of nets, number of vias) and crosstalk (delay due to coupled(More)