Jens Brandenburg

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The main goals of the 2PARMA project are: the definition of a parallel programming model combining component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable byte-code, run-time resource management policies and mechanisms as well as design space exploration methodologies for many-core computing(More)
Future LTE mobile communication systems provide for the first time low delay and high data rate and access over wireless. This enables transmission of new multimedia applications with high quality. H.264/Scalable Video Coding delivers high-quality video content with a scalable data rate, which perfectly matches with the LTE technology. The combination of(More)
The recently finalized High-Efficiency Video Coding (HEVC) standard was jointly developed by the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG) to improve the compression performance of current video coding standards by 50%. Especially when it comes to transmit high resolution video like 4K over the internet or(More)
By introducing novel algorithms in the emerging high efficiency video coding (HEVC) standard average bitrate savings of 23% have been achieved in comparison to the H.264/AVC high profile reference encoder for the all intra configuration at the cost of an additional complexity increase. This high algorithmic complexity requires the development and(More)
Real-time applications, hard or soft, are raising the challenge of unpredictability. This is an extremely difficult problem in the context of modern, dynamic, multiprocessor platforms which, while providing potentially high performance, make the task of timing prediction extremely difficult. Also, with the growing software content in embedded systems and(More)
The novel High Efficiency Video Coding (HEVC) standard targets a broad set of different video formats ranging from QVGA up to Ultra-HD (4Kp60) resolutions. Especially the high spatial and temporal resolutions combined with the high algorithmic complexity makes implementing encoders and decoders a challenging task. Existing software based implementations on(More)
HW/SW co-design and optimization requires an in-depth performance and bottleneck analysis of the developed system. Due to the increasing gap between the performance of the processing elements and the memory subsystem also memory access analysis plays an important role in this optimization task. This is especially the case for state of the art media signal(More)
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