Jeffrey W. Kellington

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Full chip statistical fault injection has been performed on a hardware emulated POWER6 platform. These results were validated against proton beam injection results. The fault isolation, error recovery and error logging capabilities of the POWER6 enabled measurement of the architectural derating factors. The proportion of errors as well as derating factors(More)
A method for statistical fault injection (SFI) into arbitrary latches within a full system hardware-emulated model is validated against particle-beam-accelerated SER testing for a modern microprocessor. As performed on the IBM POWER6 microprocessor, SFI is capable of distinguishing between error handling states associated with the injected bit flip.(More)
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