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FinFET — A Self-Aligned Double-Gate MOSFET Scalable to 20 nm

• Digh Hisamoto, Wonoh Lee, +7 authors Chenming Calvin Hu
• 2000

MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si0 4Ge0 6 as a gate… (More)

Dynamic Threshold-Voltage MOSFET ( DTMOS ) for Ultra-Low Voltage VLSI

• Fariborz Assaderaghi, Dennis Sinitsky, Stephen A. Parke, Jeffrey Bokor, Ping K. Ko, Chenming Calvin Hu
• 1997

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator… (More)

FinFET scaling to 10 nm gate length

• Bin Yu, Leland Chang, +11 authors D. Kyser
• Digest. International Electron Devices Meeting,
• 2002

While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability… (More)

Sub 50-nm FinFET: PMOS

• Xuejue Huang, Wen-Chin Lee, +11 authors Chenming Hu
• International Electron Devices Meeting 1999…
• 1999

High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOS… (More)

Complementary silicide source / drain thin-body MOSFETs for the 20 nm gate length regime

• Jakub Kedzierski, Peiqi Xuan, Erik Hyde Anderson, Jeffrey Bokor, Tsu-Jae King, Chenming Calvin Hu
• 2000

Thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15nm. Complementary low-barrier silicides were used to reduce contact and series resistance. Minimum… (More)

Sub-20 nm CMOS FinFET technologies

• Yang-Kyu Choi, Nick Lindert, +6 authors Chenming Calvin Hu
• International Electron Devices Meeting. Technical…
• 2001

A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000).… (More)

A folded-channel MOSFET for deep-sub-tenth micron era

• Digh Hisamoto, Wen-Chin Lee, +6 authors Chenming Hu
• International Electron Devices Meeting 1998…
• 1998

Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel folded channel transistor structure is proposed. The quasi-planar… (More)

Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs

• Leland Chang, Stephen Tang, Tsu-Jae King, Jeffrey Bokor, Chenming Calvin Hu
• 2000

Abstract In the nanoscale regime, the double-gate MOSFET can provide superior short-channel behavior. For this structure, device scaling issues are explored. Gate length scaling will be limited by… (More)

Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

• Nick Lindert, Lan Chang, +5 authors Chenming Hu
• IEEE Electron Device Letters
• 2001

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short… (More)

Energy-Efficient Abundant-Data Computing: The N3XT 1,000x

• Mohamed M. Sabry, Mingyu Gao, +17 authors Subhasish Mitra
• Computer
• 2015

Next-generation information technologies will process unprecedented amounts of loosely structured data that overwhelm existing computing systems. N3XT improves the energy efficiency of abundant-data… (More)

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