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Journals and Conferences
An interconnection pattern of processing elements, the cube-connected cycles (CCC), is introduced which can be used as a general purpose parallel processor. Because its design complies with present technological constraints, the CCC can also be used in the layout of many specialized large scale integrated circuits (VLSI). By combining the principles of… (More)
Examples of fruitful interaction between geometrical combinatorics and the design and analysis of algorithms are presented. A demonstration is given of the way in which a simple geometrical construction yields new and efficient algorithms for various searching and list manipulation problems.
A data structure is described which can be used for representing a collection of priority queues. The primitive operations are insertion, deletion, union, update, and search for an item of earliest priority.
| Programmable Active Memories (PAM) are a novel form of universal reconngurable hardware co-processor. Based on Field-Programmable Gate Array (FPGA) technology, a PAM is a virtual machine, controlled by a standard microprocessor , which can be dynamically and indeenitely recon-gured into a large number of application-speciic circuits. PAMs ooer a new… (More)
We introduce a representation of the <italic>computable real numbers</italic> by continued fractions. This deals with the subtle points of undecidable comparison an integer division, as well as representing the infinite 1/0 and undefined 0/0 numbers. Two general algorithms for performing arithmetic operations are introduced. The <italic>algebraic… (More)
Experimental work on reconfigurable computing has focussed on FPGAs as the only available implementation technology. While many successful systems have been built from single-bit output FPGA logic cells, there appear to be limits to this approach when compared to ASICs: low arithmetic density, reduced clock speed and low internal RAM density and bandwidth,… (More)
We detail and analyse the critical techniques which may be combined in the design of fast hardware for RSA cryptography: chinese remainders, star chains, Hensel's odd division (a.k.a. Montgomery modular reduction), carry-save representation, quotient pipelining and asynchronous carry completion adders. A PAM 1 implementation of RSA which combines all of the… (More)
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [BRV89]. Based on Field Programmable Gate Array (FPGA) technology, the PAM is a universal hardware co-processor closely coupled to a standard host computer. The PAM can speed up many critical software applications running on… (More)
We have two main purposes in this paper. First, we clarify and extend known results about computation of recursive programs, emphasizing the difference between the theoretical and practical approaches. Secondly, we present and examine various known methods for proving properties of recursive programs. We discuss in detail two powerful inductive methods,… (More)