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We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by BRV 89]. Based on Programmable Gate Array (PGA) technology, the PAM is a universal hardware co-processor closely coupled to a standard host computer. The PAM can speed up many critical software applications running on the(More)
An interconnection pattern of processing elements, the cube-connected cycles (CCC), is introduced which can be used as a general purpose parallel processor. Because its design complies with present technological constraints, the CCC can also be used in the layout of many specialized large scale integrated circuits (VLSI). By combining the principles of(More)
We establish new, yet intimate relationships between the 2adic integers 2 Z from arithmetics and digital circuits, finite and infinite, from electronics. (a) Rational numbers with an odd denominator correspond to output only synchronous circuits. (b) Bit-wise 2ading mappings correspond to combinational circuits. (c) On-line functions, 8n 2 N; x 2 2 Z : f(x)(More)
| Programmable Active Memories (PAM) are a novel form of universal reconngurable hardware co-processor. Based on Field-Programmable Gate Array (FPGA) technology, a PAM is a virtual machine, controlled by a standard microprocessor , which can be dynamically and indeenitely recon-gured into a large number of application-speciic circuits. PAMs ooer a new(More)
We detail and analyse the critical techniques which may be combined in the design of fast hardware for RSA cryptography: chinese remainders, star chains, Hensel's odd division (a.k.a. Montgomery modular reduction), carry-save representation, quotient pipe-lining and asynchronous carry completion adders. A PAM 1 implementation of RSA which combines all of(More)