Jean-Pierre Le Normand

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In this paper, two architectures for high-speed time-resolved imaging circuits in (Bi)CMOS technology are presented. The first architecture adopts the traditional for the most silicon imagers matrix configuration, where the photocharges-induced signal is processed directly in-pixel. The second approach is based on a single light detecting vector, comparable(More)
A Macropixel for photon counting integrated streak camera has been developed in a 180nm standard CMOS process. It includes a 4×4 array of Single Photon Avalanche Diodes (SPAD) acting as a small and smart SiPM (Silicon Photo Multiplier), a unique quenching circuit and a 16 bits memory for smart pixel operation. The total Macropixel size is(More)
This paper presents the state of the art of the Integrated Streak Camera (ISC) architectures in standard CMOS technology. It focuses on some of the methods required for reconstructing the luminous events profile from the chip raw data. Two main ISC architectures are presented. The first adopts the traditional for the most silicon imagers pixel array(More)
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