Jean-Paul Chaput

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In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling to nanometer processes presents many difficult challenges to CAD flows. Academic research on back-end mostly focuses on specific algorithmic issues separately. However one key issue(More)
This paper will present a methodology and flow to automate the test bench creation for automotive heterogeneous HW/SW systems, using SystemC, SystemC-AMS and IP-XACT. The UVM foundation elements such as test, environment, UVC (Universal Verification Component), transactions and associated configuration objects are introduced, which are packaged by means of(More)
Each new embedded system tends to integrate more sensors with tight software-driven control, digitally assisted analog circuits, and heterogeneous structure. A more responsive simulation environment is needed to support the codesign and verification of such complex architectures including all its digital hardware/software and analog/multi-physical aspects(More)
Hao Zou, Yasser Moursy, Ramy Iskander, Jean-Paul Chaput, Marie-Minerve Louërat. An Adaptive Mesh Refinement Strategy of Substrate Modeling for Smart Power ICs. IEEE International Symposium on Circuits and Systems (ISCAS 2016), May 2016, Montreal, Canada. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp.2358-2361, 2016,(More)
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