Jean-Michael Hartmann

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Reducing the drain voltage, V<sub>DD</sub>, is the key leverage to lower power dissipation in circuits, since the dynamic losses increase proportional to V<sub>DD2</sub> multiplied by the frequency. Presently, fully depleted silicon on insulator (FDSOI) technology sets the level pole for ultra-low power applications: At 0.6 V a clock frequency of 1 GHz has(More)
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