Jean-Marie Gauthier

  • Citations Per Year
Learn More
This paper proposes an approach to verify SysML models consistency and to validate the transformation of SysML models to VHDL-AMS code. This approach is based on two main solutions: the use of model-to-model transformation to verify SysML models consistency and writing unit tests to validate model transformations. The translation of SysML models into(More)
In this paper, we propose a SysML model and a Modelica simulation of an air-jet conveyor for micro objects. Indeed, modeling and simulation are part of verification & validation activities, which are important tasks during the conception of a complex system. This article focuses mainly on the modeling and simulation of air-jet nozzles and on their(More)
This paper presents the context, motivations and perspectives of my PhD research about model-based testing for real-time and embedded systems using SysML. This work is based on an existing model-based approach which has been proposed during the VETESS project. This approach aims to generate tests for embedded systems. In this paper, we identify areas of(More)
  • 1