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- Jean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki
- IACR Cryptology ePrint Archive
- 2010

We propose compact architectures of the SHA3 candidates BLAKE-32 and BLAKE-64 for several FPGA families. We harness the intrinsic parallelism of the algorithm to interleave the computation of four instances of the Gi function. This approach allows us to design an Arithmetic and Logic Unit with four pipeline stages, and to achieve high clock frequencies.… (More)

This paper describes the design of a fast multi-core library for the cryptographic Tate pairing over supersingular elliptic curves. For the computation of the reduced modified Tate pairing over F3509 , we report calculation times of just 2.94 ms and 1.87 ms on the Intel Core2 and Intel Core i7 architectures, respectively. We also try to answer one important… (More)

This paper describes the design of a fast software library for the computation of the optimal ate pairing on a Barreto–Naehrig elliptic curve. Our library is able to compute the optimal ate pairing over a 254-bit prime field Fp, in just 2.33 million of clock cycles on a single core of an Intel Core i7 2.8GHz processor, which implies that the pairing… (More)

- Jean-Luc Beuchat
- IPDPS
- 2003

This paper is devoted to the study of number representations and algorithms leading to efficient implementations of modular adders and multipliers on recent Field Programmable Arrays. Our hardware operators take advantage of the building blocks available in such devices: carrypropagate adders, memory blocks, and sometimes embedded multipliers. The first… (More)

- Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Francisco Rodríguez-Henríquez
- IACR Cryptology ePrint Archive
- 2008

In this article we propose a study of the modified Tate pairing in characteristics two and three. Starting from the ηT pairing introduced by Barreto et al. [1], we detail various algorithmic improvements in the case of characteristic two. As far as characteristic three is concerned, we refer to the survey by Beuchat et al. [4]. We then show how to get back… (More)

In this paper, we propose a modified ηT pairing algorithm in characteristic three which does not need any cube root extraction. We also discuss its implementation on a low cost platform which hosts an Altera Cyclone II FPGA device. Our pairing accelerator is ten times faster than previous known FPGA implementations in characteristic three.

- Jean-Luc Beuchat, Jacques-Olivier Haenni, Eduardo Sanchez
- IPPS/SPDP Workshops
- 1998

This paper aims at comparing multiplication algorithms over Fpm on FPGA. Contrary to previous surveys providing the reader with an estimate of both area and delay in terms of XOR gates, we discuss placeand-route results which point out that the choice of an algorithm depends on the irreducible polynomial and on some architectural parameters. We designed a… (More)

Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. Software implementations being rather slow, the study of hardware architectures became an active research area. In this paper, we first study an accelerator for the ηT pairing over F3[x]/(x + x… (More)

- Diego F. Aranha, Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals
- IACR Cryptology ePrint Archive
- 2010

This article presents a novel optimal pairing over supersingular genus-2 binary hyperelliptic curves. Starting from Vercauteren’s work on optimal pairings, we describe how to exploit the action of the 2-th power Verschiebung in order to further reduce the loop length of Miller’s algorithm compared to the genus-2 ηT approach. As a proof of concept, we detail… (More)