Jean-François Naviner

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0026-2714/$ see front matter 2008 Elsevier Ltd. A doi:10.1016/j.microrel.2008.07.002 * Corresponding author. Address: Institut TELECO CNRS, COMELEC Departement, 46 Rue Barrault, 75 0145817103; fax: +33 0145804036. E-mail address: denis.teixeira@telecom-paristech.f As integrated circuits scale down into nanometer dimensions, a great reduction on the(More)
A Sample and Hold circuit using the 0.6 pm technology for low frequency application is presented. This circuit is based on a specific memory base cell that reduces the error caused by the output conductance. It works with a 3.3 V supply voltage, offers high-resolution and low power dissipation. Simulations results presented a -77.6 dB harmonic distortion(More)
Due to the expected increase of defects and errors in circuits based on deep submicron technologies, reliability has become an important design criterion. As reliability improvement is generally achieved by adding redundancy, identify and classify critical blocks of a circuit is a major concern. This work presents two new classification methods regarding(More)