Jean-François Naviner

Learn More
Due to the expected increase of defects and errors in circuits based on deep submicron technologies, reliability has become an important design criterion. As reliability improvement is generally achieved by adding redundancy, identify and classify critical blocks of a circuit is a major concern. This work presents two new classification methods regarding(More)
This paper deals with the problem of clock skew errors in time-interleaved analog-to-digital converters. Deterministic sample-time errors between time-interleaved channels generate nonlinear distortion and degrade SFDR. We propose a fully digital calibration method that uses, on the one hand, adaptive FIR filters to reconstruct a correctly sampled signal(More)
—Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context we introduce a cost-aware methodology for selective hardening of combinational logic cells. The methodology is(More)