Jean DaRolt

We present a survey on the state-of-the-art in scan-based side-channel attacks on symmetric and public-key cryptographic hardware implementations, both in the absence and presence of advanced DfT structures. Expand

The conflict between security and testability is still a concern of hardware designers. Expand

Scan chains insertion is the most common technique to ensure the testability of digital cores, providing high fault coverage. Expand

In this paper we propose a novel architecture that implements a secure JTAG interface. Expand

In this paper we present a smart test controller that is able to prevent all known scan attacks. Expand

We show that DfT structures, regardless of their nature, do not inherently enhance security and that specific additional countermeasures are still needed. Expand

We present a new generic scan attack that covers a wide range of industrial test infrastructures, including spatial response compressors. Expand

We propose a novel DfT technique for scan design that provides testing facilities both at production time and over the course of the circuit's life. Expand

This paper proposes a new scan-based side-channel attack on RSA public-key cryptographic implementations in the presence of advanced Design for Testability (DfT) techniques. Expand

This paper presents a scan-based attack on hardware implementations of Elliptic Curve Cryptosystems (ECC). Expand