Sort by:

• Highly Influential Citations
• Citations
• Acceleration
• Velocity
• Recency

Learn More

Secure JTAG Implementation Using Schnorr Protocol

• Amitabh Das, Jean DaRolt, +6 authors Ingrid Verbauwhede
• J. Electronic Testing
• 2013

The standard IEEE 1149.1 (Test Access Port and Bou ndary-Scan Architecture, also known as JTAG port) provides a useful interface for embedded systems development, debug, and test. In an… (More)

Scan Attacks and Countermeasures in Presence of Scan Response Compactors

• Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
• 2011 Sixteenth IEEE European Test Symposium
• 2011

The conflict between security and testability is still a concern of hardware designers. While secure devices must protect confidential information from unauthorized users, quality testing of these… (More)

A novel differential scan attack on advanced DFT structures

• Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
• ACM Trans. Design Autom. Electr. Syst.
• 2013

Scan chains insertion is the most common technique to ensure the testability of digital cores, providing high fault coverage. However, for ICs dealing with secret information, scan chains can be used… (More)

A smart test controller for scan chains in secure circuits

• Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
• 2013 IEEE 19th International On-Line Testing…
• 2013

Structural testing is one important step in the production of integrated circuits. The most common DIT technique is the insertion of scan-chains, which increases the observability and the… (More)

New security threats against chips containing scan chain structures

• Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
• 2011 IEEE International Symposium on Hardware…
• 2011

Insertion of scan chains is the most common technique to ensure observability and controllability of sequential elements in an IC. However, when the chip deals with secret information, the scan chain… (More)

Test Versus Security: Past and Present

• Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
• IEEE Transactions on Emerging Topics in Computing
• 2014

Cryptographic circuits need to be protected against side-channel attacks, which target their physical attributes while the cryptographic algorithm is in execution. There can be various side-channels,… (More)

Are advanced DfT structures sufficient for preventing scan-attacks?

• Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
• 2012 IEEE 30th VLSI Test Symposium (VTS)
• 2012

Standard Design for Testability (DfT) structures are well known as potential sources of confidential information leakage. Scan-based attacks have been reported in publications since the early 2000s.… (More)

A New Scan Attack on RSA in Presence of Industrial Countermeasures

• Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
• COSADE
• 2012

This paper proposes a new scan-based side-channel attack on RSA public-key cryptographic implementations in the presence of advanced Design for Testability (DfT) techniques. The attack is performed… (More)

Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison

• Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
• IEEE Transactions on Very Large Scale Integration…
• 2014

Hardware implementation of cryptographic algorithms is subject to various attacks. It has been previously demonstrated that scan chains introduced for hardware testability open a back door to… (More)

A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures

• Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
• 2012 IEEE International Symposium on Defect and…
• 2012

This paper presents a scan-based attack on hardware implementations of Elliptic Curve Cryptosystems (ECC). Several up-to-date Design-for-Testability (DfT) features are considered, including response… (More)

• ‹
• 1
• 2
• ›