Jean-Claude Herluison

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This paper describes a high-level multi-HDL design process applied to an industrial design of a single chip Videophone Codec. It makes use of many state-of-the-art design tools and methods: • Behavioural VHDL control path synthesis for the controller of the Codec motion estimator. • Behavioural DSP synthesis from Silage to generate an application-specific(More)
This paper presents the design of a Videophone CoderDecoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (complex communication protocol) with a Data Flow Dominated part (high throughput computations) makes this circuit di cult to be synthesized by a single HLS tool. The combination of two(More)
This paper presents the design of a Videophone Coder-Decoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (complex communication protocol) with a Data Flow Dominated part (high throughput computations) makes this circuit diicult to be synthesized by a single HLS tool. The combination of two(More)
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