Jean-Christophe Prévotet

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— Reconfigurable resources are more and more envisaged inside System-on-Chip designs for facing with embedded computing power constraints. Moreover, a high level of flexibility of such platforms is required and can only be achieved with embedded software and real-time operating systems (RTOS) services. Unfortunately, this leads to very complex and(More)
High-energy physics experiments require high-speed triggering systems capable of performing complex pattern recognition at rates of Megahertz to Gigahertz. Neural networks implemented in hardware have been the solution of choice for certain experiments. The neural triggering problem is presented here via a detailed look at the H1 level 2 trigger at the HERA(More)
— Multiprocessor Systems-on-Chip (MPSoC) are becoming the standard high performance Digital Signal Processing (DSP) systems. Hardware complexity abstraction is needed to enable efficient MPSoC programming. A major challenge of MPSoC programming is efficiently handling the combination of new features necessary in a MPSoC operating system: load balancing and(More)
This paper deals with the implementation of a new recon-figurable architecture for the computation of Fast Fourier Transform (FFT) in the context of digital terrestrial television broadcasting (DTTB). The proposed architecture allows more possibilities in the choice of the FFT size. In this paper, two algorithms (Radix algorithm and Winograd Fourier(More)
Nowadays, demands for high performance keep on increasing in the wireless communication domain. This leads to a consistent rise of the complexity and designing such systems has become a challenging task. In this context, energy efficiency is considered as a key topic, especially for embedded systems in which design space is often very constrained. In this(More)