Jean-Christophe Crebier

Learn More
—This article analyzes the effects of parasitic capacitances in the series connection of IGBT, which exist naturally due to gate driver and power circuit geometry. Two solutions, that can be combined, are proposed to minimize these effects in order to achieve a better voltage balancing. The first one is based on gate driver self-powering technique. The(More)
—The paper focuses on a new generation of power modules, trying to optimize the tradeoff between thermal and EMI managements. At the same time, the packaging approach is considered in order to simplify the implementation of the power dies while improving the reliability of the structure. The approach considers the hybrid integration of the power dies, one(More)
The paper deals with the management and the reduction of conducted common mode EMI noise in power converters. Especially, it is presented how complementary P-N MOSFET structures, used in a specific manner, are able of great and natural common mode current reductions. The advantages obtained by the use of complementary MOSFET topologies are balanced with the(More)
—This study deals with the power electronics packaging and the needs for additional knowledge about electrical pressed contact behavior. For this, a measure bench has been realized. It is able to characterize the pressed interface between a metal electrode and a power chip as a function of the clamping force (0-8000N) and the temperature (up to 100°C).(More)
This paper deals with the design, the realization and the characterization of an integrated converter for low voltage and low power, isolated applications (3.3 V, 1 W). It is based on the association of two generic silicon dies performing DC to AC and AC to DC operations. The power dies are designed in CMOS technology and operate at high frequency (1 MHz)(More)