Jean-Baptiste Begueret

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A methodology is proposed to design Lamb wave resonators and filters for the intermediate frequencies. Two RF receiver architectures employing these devices are presented. Indeed, by simultaneously offering a high quality factor (above 1000) and above-IC integration, Lamb wave devices can advantageously replace standard SAW IF filters. The filters presented(More)
This paper presents the digitizer developed for the second phase of the ALMA (Atacama Large Millimeter Array) project. This ASIC is a monolithic A/D converter implemented in a BiCMOS 0.25 /spl mu/m. SiGe process from STMicroelectronics. The main features of the ADC are a 3 bit resolution (8 quantization levels), an input bandwidth from 2 to 4 GHz with 4 GHz(More)
A novel LNA topology with a transformer-based input integrated matching is proposed and its application to the 60-GHz millimeter-wave design in bulk CMOS 65 nm technology is reported. This topology exploits a novel technique to realize the input integrated matching (simultaneous input impedance and minimum noise matching to the source resistance) in cascode(More)
this work proposes an Ultra Low Power (ULP) digitally controlled LNA dedicated to Wireless Sensor Networks (WSN) implemented in a 0.13µm CMOS technology. Both optimized topologies and reconfigurable issues are investigated to save power consumption. Based on a self biased inverter, the circuit, operating under 0.6V, consumes 120µW and achieves(More)
This paper presents a novel method for analyzing the analog specifications of bandpass sampling (BPS) receivers. The method guarantees fast convergence to the required performance and can be exploited to study the best configurations for a given constraint (eg. power, integration) using different noise degradation distributions. A wide-band system-level(More)
This paper presents the trade-offs facing bandpass sampling receiver architectures for ultra-low power applications. To illustrate these trade-offs, three different bandpass sampling receiver architectures are specified for the Bluetooth low energy and 802.15.4 standards using a novel system design methodology which guarantees fast convergence to a(More)
This paper explores new capabilities brought on by Independently Driven Double Gate CMOS transistors (IDGMOS) for analog baseband design. Since the gates are disconnected, the corresponding channels are coupled resulting in a dynamic threshold voltage tuning. This operation mode is exploited to create new analog functions and low-voltage circuits. A current(More)
A novel technique for the stabilization of local oscillators is presented in this paper based on the combination of a Phase Locked Loop (PLL) and Delay Locked Loop (DLL) architecture. On one hand, phase noise performances are improved taking advantage of the both architecture and more particular to the non-accumulation of random timing jitter. On the other(More)
The next generation of mobile terminals is faced with the emergence of the software-defined radio (SDR) concept. The communication devices tend to provide various wireless services through a multi-functional, multi-mode and multi-standard terminal. The SDR concept aims at designing a re-configurable radio architecture accepting all cellular or noncellular(More)