Jayawan H. B. Wijekoon

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Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this(More)
A silicon neuron circuit that produces spiking and bursting firing patterns, with biologically plausible spike shape, is presented. The circuit mimics the behaviour of known classes of cortical neurons: regular spiking (RS), fast spiking (FS), chattering (CH) and intrinsic bursting (IB). The paper describes the operation of the circuit, provides simulation(More)
— This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 µm CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a(More)
—The paper presents a silicon neuron circuit that mimics the behaviour of known classes of biological neurons. The circuit has been designed in a 0.35µm CMOS technology. The firing patterns of basic cell classes: regular spiking (RS), fast spiking (FS), chattering (CH) and intrinsic bursting (IB) are obtained with a simple adjustment of two biasing(More)
This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and(More)
— This paper proposes a silicon neuron circuit which uses a slow-variable controlled leakage term to extend the repertoire of spiking patterns achievable in an integrate and fire model. The simulations reveal the potential of the circuit to provide a wide variety of neuron firing patterns observed in neocortex, including adapting and non-adapting, regular(More)
— This paper describes a synapse circuit that approximately implements the dynamics of the dopamine (DA) modulated synapse proposed by Izhikevich (2007). The dynamics of the model, based on 'eligibility traces' generated according to a spike-timing-dependent plasticity (STDP) rule, ensure that causal pre-/post-synaptic spiking activity in the time preceding(More)
— This paper presents an analogue VLSI circuit intended to be used in a neural network architecture that closely resembles the small-scale laminar micro-circuits of the neocortex. The Cortical Neural Layer (CNL) chip comprises of 120 reconfigurable cortical neurons and 7,560 synapses. The neurons can be configured to produce regular spiking, fast spiking,(More)
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