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We address the problem of register optimization that arises during high-level synthesis from modular hierarchical behavioral specifications. Register optimization is the process of grouping carriers such that each group can be safely allocated to a hardware register. Global register optimization by inline expansion involves flattening the module hierarchy(More)
VHDL permits design descriptions with communicating multiple processes and provides signal assignments and wait statements to facilitate coordination and communication among the processes. These constructs lead to concise behavioral speciications but make controller generation in high level synthesis diicult. Current work on synthesis from VHDL restricts(More)
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