Jay Im

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In 3-D interconnect structures, process-induced thermal stresses around through-silicon-vias (TSVs) raise serious reliability issues such as Si cracking and performance degradation of devices. In this study, the thermo-mechanical reliability of 3-D interconnect was investigated using finite element analysis (FEA) combined with analytical methods. FEA(More)
In this paper we investigated the interfacial delamination of through silicon via (TSV) structures under thermal cycling or processing. First finite element analysis (FEA) was used to evaluate the thermal stresses and the driving force of TSV delamaination. Then, the modeling results were validated by analytical solutions of the crack driving force deduced(More)
Mobility and Dit distributions for p-channel MOSFETs with HfO2/LaGeOx passivating layers on germanium " Stubborn " triaminotrinitrobenzene: Unusually high chemical stability of a molecular solid to 150 GPa Stress migration risk on electromigration reliability in advanced narrow line copper interconnects Stress migration model for Cu interconnect reliability(More)
—This paper investigates two key aspects of thermomechanical reliability of through-silicon vias (TSV) in 3D interconnects. One is the piezoresistivity effect induced by the near surface stresses on the charge mobility for p-and n-channel MOSFET devices. The other problem concerns the interfacial delamination induced by thermal stresses including the pop-up(More)
In this paper, temperature-dependent thermal stresses in Cu TSVs are measured by combining the bending beam experiment with a finite element analysis (FEA). The bending beam technique measures the averaged bending curvature induced by the thermal expansion of a periodic annular Cu TSV array. The structural complexity of the blind annular TSV necessitated(More)
A kinetic analysis was formulated for electromigration enhanced intermetallic evolution of a Cu–Sn diffusion couple in the Sn-based Pb-free solder joints with Cu under bump metallurgy. The simulated diffusion couple comprised the two terminal phases, Cu and Sn, as well as the two intermetallic phases, Cu 3 Sn and Cu 6 Sn 5 , formed between them. The(More)
Three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective approach to overcome the wiring limit beyond the 32 nm technology node. Due to the mismatch of thermal expansion between the via material and Si, thermal stresses ubiquitously exist in the integrated 3-D structures. The thermal stresses can be significant to(More)
—An analytical approach to predict initiation and growth of interfacial delamination in the through-silicon via structure is developed by combining a cohesive zone model with a shear-lag model. Two critical temperatures are predicted for damage initiation and fracture initiation, respectively. It is found that via extrusion significantly increases beyond(More)